Low Complexity, High-Performance Ternary Full Adder Using CNTFET Technology

Key Points

• Existing circuit designs often struggle with efficiency in ternary logic, and this new approach shows promise.
• The proposed full adder demonstrates a significant reduction in complexity while maintaining high performance metrics.
• Analysis drawn from CNTFET technology enhances energy efficiency in emerging electrical circuits with lower power consumption.
• Potential applications of this design may expand the capabilities of modern computing systems and integrated circuits.