Enhancing Electronic Design Automation with Large Language Models: A Taxonomy, Analysis, and Opportunities

The escalating complexity of electronic systems and persistent bottlenecks in traditional Electronic Design Automation (EDA) workflows demand new approaches to improve design cycle efficiency. Large Language Models (LLMs) have emerged as a powerful technology capable of significantly enhancing various EDA tasks. This paper presents a comprehensive analysis of LLM integration in EDA. Its primary contribution is a structured taxonomy of applications based on their core function: Generation, Analysis/Interpretation, Verification/Debugging, Optimization, and Interaction. Drawing upon recent research, industry adoption, and performance benchmarks, the paper examines key areas including Hardware Description Language (HDL) generation, specification analysis, verification automation, and tool control. Commercial platforms (e.g., Cadence ChipGPT, Synopsys.ai Copilot) and open-source models (e.g., CodeV, RTLCoder) are analyzed. By synthesizing benchmark results (e.g., VerilogEval, RTLLM, AssertEval), deployment strategies such as on-premise versus cloud and Retrieval-Augmented Generation (RAG), and key challenges—including correctness versus Quality-of-Result (QoR), data scarcity, and IP protection—this paper identifies current limitations and future opportunities. These include the development of domain-specific LLMs, enhanced agentic systems, multi-modal capabilities, and improved EDA-specific benchmarks.