What question did this study set out to answer?

The aim is to simulate and analyze total ionizing dose effects on a 130 nm CMOS processor, focusing on leakage currents.

January 22, 2026Open Access

Total Ionizing Dose Effect Simulation Study on 130 nm CMOS Processor

Key Points

The aim is to simulate and analyze total ionizing dose effects on a 130 nm CMOS processor, focusing on leakage currents.
Utilized Sentaurus TCAD software for device-level simulations of 130 nm NMOS transistors.
Analyzed effects of bias conditions, channel width, and irradiation dose.
Developed a Verilog-A compact model for NMOS transistors based on TCAD simulations.
Integrated the model into the SPICE netlist for system-level TID simulations.
Identified the processor's failure threshold and corresponding failure mechanism.
Noted an increase in power supply current with irradiation dose.

Abstract

This paper reports the results of a system-level total ionizing dose (TID) effect simulation study on a SMIC 130 nm LEON2 processor. Firstly, the device-level simulations of the 130 nm NMOS transistors are performed using the Sentaurus TCAD software to analyze the effects of a bias condition, channel width, and irradiation dose on a TID-induced leakage current. Based on the TCAD simulation results, a Verilog-A-based compact model is developed for NMOS transistors to describe the TID-induced leakage current, and it is then embedded into target nodes of the SPICE netlist for the LEON2 processor, enabling system-level TID simulations. The simulation results reveal the processor’s failure threshold and corresponding failure mechanism; meanwhile, the increase in the power supply current with the irradiation dose is also observed. The research reported in this paper can provide beneficial guidance for radiation performance evaluation and radiation hardening by design (RHBD) in 130 nm bulk CMOS processors.

Total Ionizing Dose Effect Simulation Study on 130 nm CMOS Processor

Key Points

Abstract

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