What question did this study set out to answer?

The aim is to present a methodology for efficient hardware design using a higher-order approach in neural networks.

February 5, 2026

Higher-order HDL: Applied to MLP neural network hardware implementation

SGSamuel GarciaCentre National de la Recherche Scientifique MZMingjun ZhangJiangnan University

Key Points

The aim is to present a methodology for efficient hardware design using a higher-order approach in neural networks.
Developed hardware architecture using higher-order coding with TCL and VHDL
Implemented an artificial neural network (MLP) on FPGA
Customized the number of layers, layer sizes, synaptic signals, and activation functions
Achieved faster development of neural network applications
Demonstrated a fully generic multilayer perceptron model
Highlighted higher flexibility compared to conventional VHDL methodology

Abstract

In this article, we describe a methodology for the rapid implementation of a hardware architecture using a higher-order approach. This methodology uses a combination of TCL and VHDL for higher-order coding (i.e. code produced by code) and is supported by industry-standard HDL development tools. To explore this methodology, we used an FPGA implementation of an artificial neural network (ANN) as a guinea pig application. This enabled us to produce a fully generic multilayer perceptron model where the number of layers, the size of each layer, the types of synaptic signals and the activation function are easily customizable. Not only does this approach make the development of such an application faster, but the high degree of genericity of the model cannot be achieved with conventional VHDL methodology. This article presents feedback from our first steps with this methodology and its application to MLP hardware architecture. Index Terms—VHDL, TCL, Artificial Neural Networks, Multilayer Perceptron, higher-order programming, Methodology

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