Materials Design Principles for Large Memory Windows: Coercive Voltage Engineering in Ferroelectric– Dielectric Heterostructures

ABSTRACT The integration of dielectric inserts into hafnia‐based ferroelectric stacks has emerged as a promising route to expand memory windows in ferroelectric NAND. However, the physical origin of the associated coercive voltage enhancement has remained unclear. Here, we resolve this long‐standing question by demonstrating that coercive voltage enhancement originates from resistive voltage division between the ferroelectric and dielectric layers, governed primarily by leakage in both layers. Combining Preisach modeling, defect‐based Ginestra simulations, and polarization switching experiments with external leaky dielectrics, we show that minimizing leakage in the dielectric layer ‐ intrinsically through wide‐bandgap, low‐electron‐affinity dielectrics or extrinsically by reducing defect densities ‐ provides a universal design principle for coercive voltage control. Importantly, nucleation‐limited switching kinetics remain unchanged across the heterostructures, confirming that the enhancement is driven by resistive voltage division rather than trap‐assisted mechanisms. This discovery establishes a straightforward framework for engineering large memory windows using ferroelectric–dielectric heterostructures, thereby enabling multi‐level (TLC/QLC) operation in 3D NAND. Beyond memory applications, our findings also explain the contrasting behaviors of fluorite‐ vs. perovskite‐based ferroelectric–dielectric systems, offering fundamental guidance for interfacial materials design in next‐generation electronic devices.