Implementation of Adder Circuits using Majority Functions on Memristor Crossbar

The integration of both memory and computation within memristive devices has emerged as a promising approach in the domain of in-memory computing (IMC). Among various architectures, memristor-based crossbars offer high packing density, scalability, and compatibility with CMOS technology, enabling not only dense storage but also efficient implementation of Boolean logic functions. Majority logic, in particular, has shown superior efficiency over conventional logic primitives across several nanotechnologies. This work presents an adder design leveraging the majority logic function (MJF), including the realization of a full adder and a ripple carry adder directly within the IMC framework. The design assumes the availability of both nominal and complementary input data within the crossbar, allowing computation to be performed entirely in memristors. To mitigate the sneak path problem and associated read disturbances, we employ a one-transistor-one-memristor (1T1R) crossbar structure using 45 nm nMOS transistors in conjunction with the VTEAM memristor model. Furthermore, we propose a resource-constrained mapping technique for implementing arbitrary logic functions using MJF within the 1T1R crossbar. Simulation results demonstrate substantial performance gains, achieving up to 90% reduction in computation steps and 70% improvement in memristor utilization compared to existing IMC approaches.