The substantially lower breakdown electric field of Si compared to GaN necessitates thick buffer layers in Si-based GaN power devices for medium-voltage applications, significantly increasing cost. Recently, sapphire substrates, offering high electrical insulation and excellent mechanical strength, have emerged as a promising alternative. In this work, we demonstrate a CMOS-compatible process for sapphire-based GaN MIS-HEMTs utilizing a thin buffer layer. The fabricated devices with a WG of 20.4 mm and an LGD of 24 μm achieve a high off-state breakdown voltage >1650 V and a maximum on-state current > 4.1 A, with tight statistical distributions of VTH and RON across the wafer. Furthermore, statistical characterization results of dynamic RON and leakage current under electrical stress conditions at both room temperature and 150 °C, confirm operational viability at high temperatures. Finally, long-term reliability for 650 V operation is validated by high-temperature reverse bias (HTRB) accelerated aging tests.
Chen et al. (Wed,) studied this question.