A high-frequency reference clock (CKREF) adopted in charge-pump-based phase-locked loops (CPPLLs) can reduce the feedback division factor, thereby alleviating the noise influence from the phase/frequency detector (PFD), charge pump (CP), and loop filter (LF). However, the PFD, serving as the front end of CPPLLs, suffers from an enlarged blind zone (BZ) that consequently reduces its average gain (KPFD) during high-frequency operation. To address this issue, this work proposes two pulsed-latch-based PFDs (PLPFDs) that mitigate the BZ and enhance KPFD. Through analysis of the relationship between the clock frequency (fCK), the reset loop delay, and the pulsewidth of the clock signal, these two PLPFDs can operate in either a higher-fCK mode or a lower-BZ mode, depending on whether pulse generators (PGs) are used. Implemented using a 0.18-μm CMOS process, HSPICE simulation results demonstrate an operating frequency range of 1.8-3.4 GHz with lower power consumption in the higher-fCK mode, and 0.5-1.7 GHz with a minimized BZ of 0.010-0.027 π in the lower-BZ mode. In particular, these PLPFDs can be readily integrated into CPPLLs that employ various high-frequency CKREF, enabling fast acquisition for advanced communication systems.
Zong-Yi Yang (Thu,) studied this question.