FPGA Implementation and Performance Evaluation of Classic PID, IMC and DTC for BLDC Motor Control

Brushless DC (BLDC) motors are widely used in mobile robotics and off-road vehicles due to their high efficiency, reliability, and compactness. However, achieving robust, high-performance speed control in embedded environments remains challenging due to nonlinearities, dead-time effects, parameter uncertainties, and strict real-time constraints. This paper presents a comprehensive experimental study of classical and robust control strategies for BLDC motor speed control, fully implemented on an FPGA platform. Classical PI and PID controllers tuned using Ziegler–Nichols, Cohen–Coon, and Chien–Hrones–Reswick methods are first investigated and discretized using both Zero-Order Hold (ZOH) and Tustin (bilinear) approximations. Model-based approaches, including IMC-based PID controllers, are then introduced to enhance robustness. In addition, a robust two-degree-of-freedom dead-time compensator (DTC) is implemented to explicitly address dead-time uncertainties inherent to inverter-based motor drives. All controllers are implemented using fixed-point arithmetic on a Xilinx Nexys A7 FPGA and validated experimentally on a BLDC motor test bench representative of semi-autonomous robotic applications. Performance is evaluated through time-domain responses and quantitative indices, including ISE, ITAE, I, control effort, and FPGA resource utilization. Experimental tests under controlled DC bus voltage disturbances are conducted to assess disturbance rejection capability and robustness under realistic operating conditions. Experimental results demonstrate that Tustin discretization consistently improves tracking performance, while IMC-PID and DTC strategies provide superior robustness against dead-time and modeling uncertainties, making them particularly suitable for embedded FPGA-based motor control.