One of the most promising novel devices expected in the post-Moore era is the single flux quantum (SFQ) technology. In particular, studies suggest that a neural network accelerator (NNA) could outperform CMOS counterparts in terms of performance and power efficiency. However, as these studies rely on model-based estimation, the feasibility of high-speed operation is yet to be verified. In this paper, we have prototyped an NNA using a current fabrication process to verify its feasibility. As a result, we have achieved an operating frequency of 35 GHz, which is higher than that of CMOS accelerators, but lower than the 52 GHz estimated in previous work. Considering the timing constraints of SFQ logic gates, it is possible to achieve a higher frequency. Therefore, we have revisited the conventional design guidelines, aiming for faster operation. The NNA designed using the improved design methodology has been confirmed to be capable of operating at an unprecedentedly high frequency of 100 GHz through post-layout simulation. This accelerator is too large to be fabricated because we extended the bit-width of its arithmetic unit to perform the method is applicable for more complex circuits, so we are fabricating an arithmetic unit, the most complicated part in this NNA.
Ishikawa et al. (Thu,) studied this question.