3D Stochastic geometry framework For IRS-assisted hybrid beamforming in massive MIMO under imperfect CSI

Abstract This paper presents a three-dimensional (3D) stochastic geometry framework to analyze intelligent reflecting surface (IRS) – assisted hybrid beamforming in massive MIMO downlink systems under imperfect channel state information (CSI). Leveraging stochastic geometry, user locations are modeled by a three-dimensional homogeneous Poisson point process (3D-HPPP), enabling tractable spatial averaging of distance distributions, angle spreads, and interference statistics. Both the direct BS–UE link and the cascaded BS–IRS–UE link incorporate geometry-dependent estimation errors that are correlated with spatial positions and LoS probabilities. We derive robust lower bounds on the per-user Signal-to-Interference-plus-Noise Ratio (SINR) and the corresponding sum spectral efficiency (SE) by treating channel estimation errors as additional interference, yielding tractable expressions that quantify the degradation across SNR, CSI error variance, and IRS size. A holistic evaluation covering SE, energy efficiency (EE), and bit error rate (BER) reveals four key insights: (i) finite IRS phase resolution induces BER floors at high SNR, with diminishing returns beyond 3–4 bits; (ii) an IRS-assisted hybrid architecture approaches the performance of a fully digital system while using far fewer RF chains; (iii) CSI errors dominate performance at high SNR, highlighting the need for accurate channel acquisition; and (iv) EE is non-monotonic in the number of IRS elements due to IRS controller/circuit power, yielding an EE-optimal IRS size. Notably, under moderate CSI errors (e. g. , ₑ²=0. 05 σ e 2 = 0. 05 at 20 dB), the system retains over 80% of the perfect-CSI SE. Overall, the framework offers design guidelines for robust, hardware-aware IRS deployments in 5G-Advanced and 6G networks. Our results demonstrate a ’hardware-CSI crossover point’: improving IRS phase resolution beyond 3 bits yields negligible gains unless CSI estimation error variance is below ₑ² = 0. 01 σ e 2 = 0. 01, dictating a specific order of priority for hardware upgrades.