The most widely used solution for III-V/Si hybrid integration for SWIR imagers is the flip-chip bonding of III-V sensor dies to Si Read-out dies using Indium bump technology. However, this ball bonding faces scaling limitations when approaching a pitch less than 10micron due to technology limitations 1,2. The use Cu/Ni/Sn micro-bumps has enabled mainstream silicon-to-silicon die bonding technology to scale to very small pitches 3. Hybrid integration of Si and III-V dies could also benefit from the scalability of the Ni/Sn process, reducing the pitch to 10micron and below. This would enable a low-cost solution for a myriad of applications, including SWIR sensing. However, the difference in CTE between Si and III/V materials poses additional limitations on this bonding process, particularly for micro-bumps with a pitch below 10micron. In this work, we present the bonding of Ni/Sn bumps on a Si die to Au bumps on an InP substrate, and explore the process window for CTE optimization.Experimental details:The test vehicle is configured as a single large 1280x1024 array of bumps, divided into blocks with different connection schemes to evaluate daisy chains, Kelvin structures and a 512x256 yield arrays to evaluate individual bump connections. Die-to-Die bonding experiments were then performed using this layout on an S.E.T. FC300 bonder tool. The bonding parameters varied during the experiment included bonding force, bond time, the temperature of bottom and top dies, application of underfill, and ramp rate.Samples were inspected for alignment. Physical characterization such as top-down optical and SEM inspections, along with EDX analysis, were conducted on mechanically debonded samples to assess bond strength, measure misalignment due to CTE mismatch, and identify failure modes. Assemblies were also electrically tested for yield. The interwoven daisy chain structures placed at various distances from the die corners were used to evaluate open bumps in the chain as well as leakage to the neighbouring chain. These daisy chain structure provide yield info but do not pinpoint the exact location of the failure. To address this, a yield array of 512x256 bumps was placed in the layout to identify the exact locations of failing bumps. This structure can probe all the bumps in the array individually to determine whether each bump is connected or open. Finally, cross-sectional analysis was performed on selected assemblies.Results and conclusions:A morphological assessment of the bonded samples after manual debonding confirmed good material transfer at bonding temperatures in the range of 270-300C. Measurements of the alignment at different locations across the die, revealed an outward pattern corresponding to the mismatch in CTE between the Si and InP substrates. For a 1280x1024 array at 10micron pitch, this mismatch in the corner areas was found to be in the range of 2um. This poses a limit to the die size or pitch scaling. The CTE mismatch also induces strain in the assembly, resulting in a bow across the die of about 6um for a full substrate thickness of 500m for the InP die. Substrate thinning will significantly reduce this bow.The failure modes identified through electrical testing of the daisy chains include both open links in the chains, and leakage between neighbouring chains. The number of open links detected electrically does not appear to match the good material transfer observed in visual inspections. This discrepancy can be explained by failures occurring during the cooldown process due to CTE-induced strain.In conclusion, this work presents the results of the bonding process parameter DOE for Si to InP micro bumping with Ni/Sn and Au bumps, respectively. In addition to physical characterization, electrical evaluation of bonding yields was conducted. The results indicate that the die size limits this bonding approach due to the CTE mismatch between the materials.
Vereecke et al. (Tue,) studied this question.