ABSTRACT Artificial intelligence hardware accelerators are gaining increasing importance in domains such as computer vision and robotics. However, deploying Convolutional Neural Networks (CNNs) on embedded systems with constrained resources and memory continues to pose a major challenge. Motivated by the requirements of robotic vision, this paper presents a DSP‐Efficient Packing Strategy (DEPS) accelerator architecture tailored for lightweight CNNs, improving both computational throughput and hardware efficiency in real‐time robotic applications. Unlike previous FPGA designs that underutilize DSP blocks, the proposed DEPS enables the parallel execution of twelve 3‐bit multiplications within a single DSP48E2 unit. A layer‐wise pipelined mapping scheme is also proposed, which directly maps each CNN layer onto hardware without intermediate buffering, ensuring continuous computation and minimizing latency. The proposed accelerator is incorporated into an intelligent tennis serving robot, serving as the real‐time vision module for object detection. Experimental results from VGG7‐tiny and UltraNet demonstrate throughputs of 299.4 GOPS and 340.0 GOPS, respectively, alongside power efficiencies of 80.1 GOPS/W and 89.2 GOPS/W. The robotic system deployment confirms that superior DSP utilization is achieved, enabling rapid, energy‐efficient, and reliable perception. This work highlights the potential of the proposed design for application in resource‐constrained edge platforms and practical robotics.
Li et al. (Tue,) studied this question.