Scaling interconnects to increase device density is a critical bottleneck for a range of advanced packaging and heterogeneous integration strategies. Copper (Cu) is the interconnect metal of choice to fill vias but it comes with significant challenges. To perform the fill, first a diffusion barrier is applied to ensure Cu leakage does not cause breakdown between vias, then a metal seed layer ensures smooth and dense Cu electroplating. Uniform seed resistivity, correlated with thickness, is critical to produce low resistivity interconnects. State-of-the-art processes for high quality metallic films are limited to line-of-site techniques like chemical vapor deposition (CVD) or physical vapor deposition (PVD), limiting possible device pitch and architectures. When the aspect ratio increases above 10:1 or there is a shadow, typically one of the layers is missing, resulting in too thin seed for successful Cu electroplating. This deficiency creates a void or produces a thickness gradient, resulting in pinch-off at the top. Ultimately, the device fails due to high line resistance or full dielectric breakdown. Fortunately, atomic layer deposition (ALD) can produce high density and low resistivity metal films for both Cu diffusion barrier and Cu electroplating seed applications. Here we report on a total solution to this problem using only thermal ALD. Adoption of ALD of metals has been slow in the market as traditional ALD reactors can be too slow and inefficient for production requirements or require plasma for sufficient film quality. Plasma enhanced ALD (PEALD) can produce quality films at a reasonable thermal budget, unfortunately, every plasma process will have a limit to the aspect ratio that can be coated conformally. For metal ALD this is often well below 10:1. Forge Nano has demonstrated single wafer thermal ALD technology to improve the speed and efficiency of ALD metal films, enabling a production worthy process. In this work a complete Cu barrier-seed stack solution has been demonstrated on Si vias ranging from 4:1 to 25:1 aspect ratio, showing successful Cu electroplating. A SiO2 ALD film, with a deposition rate of 10 nm/min, is first deposited to provide a dielectric barrier, when applied to Si features. A novel TiN thermal ALD process at 300°C has been developed which decreases the as-deposited resistivity from ~1200 to 1 nm/min, used as a Cu diffusion layer. Finally, a high-quality Ru film has been developed with resistivity values <20 uΩ·cm at sub-10nm film thickness as the Cu seed layer. Examples will be discussed of success as a total Cu barrier/seed stack for Cu electroplating in Si trenches up to 25:1 aspect ratios and TGV up to 10:1 aspect ratios. When compared to PVD Ti/W and Cu stack, the ALD stack produces dense, void free nucleation of Cu that remains well adhered to the via while, the PVD stack has voids at the bottom of the trench from poor adhesion of electroplated Cu and narrowing at the top from a resistivity gradient within the trench, resulting in eventual pinch-off. From this comparison, it can be observed that the Ru provides sufficient adhesion for Cu electroplating and that the resistivity of the Ru/TiN stack is sufficiently low and consistent for conformal and dense Cu electroplating. We expect this work to open up higher aspect ratio interconnects and possible new device architecture to the market.
Weimer et al. (Tue,) studied this question.