This paper presents a dual-state hardware accelerator for the ChaCha20 stream cipher, optimized for secure and low-latency communication in connected and automated vehicles (CAVs). The proposed dual-state ChaCha20 (DSCC20) architecture employs an interleaving mechanism that alternately processes two independent states, thereby eliminating idle cycles between column and diagonal rounds and keeping the round hardware fully utilized. With only one additional cycle compared to conventional single-state designs, our DSCC20 achieves substantially higher throughput while incurring minimal hardware overhead. When the design was implemented in Verilog HDL and synthesized using a 28-nm CMOS technology, the DSCC20 delivers 30.06 Gbps throughput and 904.92 Kbps/GE area efficiency at 763 MHz, outperforming baseline and earlier ChaCha20 and AES designs. Compared to software execution on general-purpose CPUs, the DSCC20 further demonstrates a decisive advantage in both throughput and area efficiency. These results confirm that the DSCC20 offers a compact and efficient ChaCha20 accelerator suited for secure and real-time communication in resource-constrained automotive systems.
Kwak et al. (Sat,) studied this question.