To overcome the main obstacle to the wide spread use of micro-organic light-emitting diode (OLED) on Si and solve device stability, imaging uniformity, and yield, much efforts have been aimed at utilizing dual-gate structure for controlling the threshold voltage of thin film transistor (TFT). However, it is still required that standard display process or its compatible process should be setup for manufacturing of ultra high-resolution display (> 3500 ppi) of extended reality (XR), augmented reality (AR), virtual reality (VR) headset to follow the continued expansion of the market and to keep device properties. In this study, we present one of the main process parameters affecting the final electrical stability of bottom gated TFT with dual gate structure in the given process sequences existing on the sub-micron complementary metal oxide semiconductor (CMOS) technologies. The measured results demonstrate that N₂ anneal (400◦C, 30 min) process after amorphous indium gallium zinc oxide (a-IGZO) deposition caused the Id-Vg characteristics of IGZO TFT with Al₂O₃ as a bottom-gate dielectric material to be much better improvement (1 × 102 times) from the 5 × 10−8 A to 5 × 10−10 A at the voltage range of 0-0.5 Vg (off state), especially the characteristics of on-off transfer curve affected on the whole for the PE-oxide gate dielectric material. Secondary ion mass spectrometry (SIMS) was used to correlate the changes in gate dielectric material with the changes in electrical behavior.
Yong et al. (Sat,) studied this question.
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