Lateral migration of charges in the charge trap layer is a critical reliability concern of modern flash memory technologies. Especially, holes are known to induce a more significant influence on retention characteristics compared to electrons. In this Letter, a unique flash memory device structure is introduced, in which the hole injection path and the lateral migration path are physically separated, enabling direct observation of lateral hole migration in the Si3N4 charge trap layer during erase operation. While not requiring the long retention measurement time, the diffusion constant of holes in the Si3N4 layer is directly extracted through simple measurements, which follows the Poole–Frenkel model with a hole trap energy depth of 2.47 eV. In addition, the trap dynamics are analyzed using the technology computer-aided design simulation, supporting the experimental and analytical results. This study provides a new method for analyzing the lateral charge migration, which is crucial for optimizing flash memory devices.
Hwang et al. (Sun,) studied this question.