The dawn of Reconfigurable Intelligent Surfaces (RIS) promises to revolutionize wireless communication by enabling dynamic control of the propagation of electromagnetic waves. However, the practical implementation of RIS demands sophisticated configuration strategies to unlock their full potential. This paper presents a hardware implementation of a Deep Learning (DL) approach to the configuration of RIS, addressing both the complexity and efficiency of the configuration process. A deep learning-based algorithm, designed to optimize the phase shifts of RIS elements and shown to enhance signal quality and system performance, is implemented on two dedicated hardware platforms based on Field-Programmable Gate Arrays (FPGA), which leads to real-time processing and adaptability. This approach leverages the inherent parallelism of FPGAs to accelerate the computationally intensive tasks associated with deep learning inference. As a matter of fact, it is possible to achieve more than 18.000 configurations per second, thus ensuring rapid and efficient RIS configuration with a novel approach within this field. • FPGA implementation of hardware accelerators of CNNs for RIS configuration on the edge. • CNN tailored for FPGA-based acceleration. • Resource and performance analysis of several architectures on Altera® and AMD FPGA devices. • Novel approach to computation of RIS configurations.
Padial-Allué et al. (Fri,) studied this question.