This study investigates the impact of non-ideal wordline sidewall angles caused by photoresist profile variation during the wordline etching process in DRAMs employing a buried-channel array transistor (BCAT) structure. Using Technology Computer-Aided Design (TCAD), a two-dimensional (2D) BCAT-based DRAM cell was modeled to analyze the resulting variations in device characteristics as well as write and hold operations. The simulation results show that increased etch slope angles lead to degradation in device performance, including failure to meet the read pass/fail criterion and data retention during the 300 ms hold interval. To mitigate these issues, we inserted a buried oxide (BOX) layer beneath the active wordline (AWL). The incorporation of the BOX layer effectively improved overall device robustness and reduced the degradation induced by non-ideal etch slopes.
Cho et al. (Tue,) studied this question.