Silicon carbide (SiC) MOSFETs are critical for next-generation power electronics, yet their reliability is challenged by alternating-current Bias Temperature Instability (AC BTI). While charge trapping and Recombination-Enhanced Defect Reaction (REDR) are known degradation pathways, the specific role of gate oxide thickness in determining the dominant mechanism remains unclear. This study investigates the degradation behaviors of SiC MOSFETs with varying oxide thicknesses under 150 kHz Dynamic Gate Stress. By maintaining a constant electric field, we decouple the effects of oxide thickness using high-frequency C-V, quasi-static gate current (IGS) characteristics, and transconductance analysis. Results reveal that thin-oxide devices exhibit parallel C-V shifts and stable transconductance, indicating degradation driven by deep-level charge trapping. Conversely, thick-oxide devices display significant C-V stretch-out, negligible IGS peak shifts, and severe transconductance degradation, accompanied by irreversible threshold voltage drift. We conclude that despite identical electric fields, the higher driving voltages in thick-oxide devices trigger severe interface state generation consistent with the REDR model, whereas thin-oxide devices are dominated by bulk oxide trapping. These findings highlight the necessity of thickness-dependent optimization strategies for SiC power devices.
Yin et al. (Wed,) studied this question.