ABSTRACT This work presents the electrical characterization of sixteen different logic gates built entirely from three‐independent‐gate reconfigurable transistors. The circuits are fabricated on full‐scale 300 mm wafers using the industrial 22 nm fully depleted silicon‐on‐insulator process of GlobalFoundries, with only minimal modifications to the baseline CMOS flow. The demonstrations include a reconfigurable 2‐2 AND‐OR‐Inverter gate and a fully functional 1‐bit adder comprising eight transistors. Quasi‐static and transient on‐wafer measurements confirm correct functionality and provide insight into the frequency limitations imposed by the current design and test setup. Finally, to explore scalability, a ripple‐carry adder is simulated based on the experimentally realized 1‐bit adder, illustrating how scaled devices and optimized layouts could enable low‐power, CMOS‐compatible applications.
Martínez et al. (Mon,) studied this question.