Design and analysis of a 6-bit 5 GS/s flash ADC for high-speed mixed-signal systems

This thesis presents the design and simulation of a 6-bit, 5GS/s Flash Analog-to-Digital Converter (ADC) in 22nm FDSOI CMOS technology. The architecture targets high-speed applications such as 5G front-ends, radar receivers, and high bandwidth instrumentation, with emphasis on energy efficiency and precision under process and environmental variations. The core building block of the ADC is a StrongARM latch comparator, optimized for regeneration speed, input-referred offset, and noise. A CDF-based transient noise methodology was employed to evaluate comparator accuracy across process corners, temperature, and different common-mode input levels. Under nominal conditions, the comparator achieved input-referred offset below 0.1mV and input-referred noise below 1mV, confirming its suitability for reliable 6-bit resolution. A single-channel 6-bit 5GS/s Flash ADC was constructed using a 63-tap reference ladder, a comparator array, synchronization flip-flops, and a Verilog-A thermometer-to-binary encoder. Pre-layout simulations confirmed correct operation, with DNL/INL within ±1LSB and no missing codes. Dynamic characterization yielded a maximum ENOB of 5.5 bits for low-to-midband inputs and 4.6 bits near Nyquist, with a power consumption of 1.4mW. To further extend the sampling rate, a two-channel time-interleaved ADC was implemented at schematic level, effectively doubling the throughput to 10GS/s. The interleaved architecture preserved functionality and maintained above 5 bits ENOB up to 1GHz input frequency, gradually decreasing to its minimum effective resolution of 3.8 bits at the Nyquist limit (5GHz), primarily due to bandwidth and clock–data alignment limits. The achieved results demonstrate the feasibility of compact and energy-efficient Flash ADCs in advanced CMOS nodes. The presented design establishes a scalable foundation for multi-channel interleaved architectures and highlights the potential of 22nm FDSOI for next-generation high-speed data converters.