Low-power arithmetic circuits play a crucial role in modern digital signal processing, embedded systems, and portable electronic devices. Among these circuits, multipliers are fundamental components that significantly influence the overall power consumption, speed, and area of Very Large Scale Integration (VLSI) systems. This work focuses on the design and analysis of an 8-bit multiplier for low-power VLSI applications with the objective of reducing power dissipation while maintaining efficient computational performance. The proposed multiplier architecture is designed using optimized partial product generation and efficient addition techniques to minimize switching activity and hardware complexity. By employing suitable low-power design strategies, the circuit achieves reduced dynamic power consumption and improved operational efficiency. The design is implemented and simulated using standard VLSI design tools, and its performance is evaluated in terms of power consumption, propagation delay, and area utilization Simulation results demonstrate that the proposed 8-bit multiplier provides better power efficiency compared to conventional multiplier architectures while maintaining acceptable speed and area performance. Therefore, the design is suitable for integration in low-power digital systems such as signal processors, portable devices, and energy-efficient embedded applications.
IJAENE (Tue,) studied this question.