High-Performance Placement for VLSI Logic Synthesis

Logic synthesis is a critical stage in the VLSI design flow. Logic synthesis methods without considering physical information would result in inferior solutions with timing violations and fail to meet high-performance design requirements. In this paper, we present an analytical placement algorithm that generates timing-friendly physical information to promote high-performance logic synthesis solutions. To address the crucial congestion issue, we first propose a fence-region-aware density model. Then, a boundary-based quadratic penalty model is constructed to ensure the cells do not violate the legal boundaries. Finally, we develop a Polak–Ribière-based placement algorithm to guide the cell movement while optimizing circuit timing. Compared to the advanced placement work, the experimental results on industrial benchmarks show that our proposed algorithm achieves 7% WNS improvement and 12% TNS optimization with 3% better logic depth.