Introduction/Objective: This work presents a fully integrated Integer-N frequency synthesizer targeting multi-standard short-range wireless protocols operating in the 2.4 GHz ISM band, including Bluetooth LE (BLE 5.4), ZigBee, Thread, and Wi-Fi coexistence. The design addresses the need for fast lock time, low residual FM, excellent spectral purity, and low-cost implementation in resource-constrained IoT applications. Methods: The synthesizer is implemented in 0.35 µm CMOS and centers on a resistorless discretetime loop filter (DT-LPF), the core innovation of this work, which eliminates on-chip resistors entirely by replacing them with a delayed charge injection mechanism using switched-capacitor networks. This approach improves stability of the loop, eliminates thermal noise associated with passive resistors, and by avoiding on-chip resistors entirely, reduces sensitivity to resistor mismatch and process variation, while enabling a more compact loop filter topology in standard CMOS processes. Complementing this, the design employs a gm/Id-optimized differential LC-VCO, a dead-zone-free tri-state PFD with 1 ns reset-path delay, and a current-scaled CML multi-modulus 2/3 divider that reduces highfrequency power dissipation. All blocks are co-optimized for 1 MHz reference frequency operation, and the system is fully designed and simulated using industry-standard EDA tools. Results: The PLL achieves a 230 MHz tuning range (2.28–2.51 GHz) with 1 MHz channel resolution, fully covering the 79-channel Bluetooth band, ZigBee/Thread channels (2.405–2.480 GHz), and the entire 2.4 GHz ISM band used by Wi-Fi. It locks in approximately 100 µs, satisfying the 30%. Despite using a lowcost 0.35 µm process, the architecture rivals advanced-node PLLs in FoM and protocol compliance. The 1 MHz reference frequency and explicit residual FM validation ensure real-world suitability for Bluetooth and ZigBee, metrics often omitted in recent works. The design demonstrates that architectural innovation can compensate for technological constraints in cost-sensitive IoT. Conclusion: The proposed synthesizer meets all essential performance metrics for ISM-band wireless protocols and demonstrates architectural efficiency and scalability. Its design offers a competitive and low-cost solution for power-sensitive short-range communication systems, particularly in cost-constrained IoT applications where advanced CMOS nodes are economically prohibitive.
Saad et al. (Wed,) studied this question.