Gallium nitride (GaN) high electron mobility transistors (HEMTs) are essential for advancing efficient, high-power, and high-frequency electronics. However, their performance and reliability are constrained by dynamic drift phenomena, such as increased ON-state resistance (RDS,on) and threshold voltage (VTH) shifts, arising from charging and transport mechanisms within the device. A deep understanding of these underlying physical processes is crucial for predicting device behavior under realistic operating conditions and for guiding improvements in design, epitaxy, and processing. A novel microsecond-resolution electrical characterization platform has been developed, enabling precise investigation of transient charging processes under both back-gating and OFF-state stress conditions. Combined with a diverse portfolio of tailored GaN test structures, this platform allowed the isolation of layer-specific effects within the complex multilayer device stack. Key findings include the development of a gate voltage dependent method to distinguish buffer trapping from surface trapping based on characteristic recovery time constants, enabling the estimation of degradation contributions from different device regions. Under uniform vertical electric fields during back-gating, distinct processes in the GaN buffer layers were identified and analyzed. An analytical back-gating model was formulated to describe field- and charge-dependent leakage currents, successfully reproducing characteristic behavior. During OFF-state stress, VTH measurements revealed direct evidence of lateral hole transport in the carbon-doped GaN (GaN:C) layer, which plays a critical role in RDS,on behavior. The RDS,on increase at moderate drain biases is attributed to newly proposed negative charging mechanisms, arising from hole accumulation under the gate. At higher drain biases, lateral hole transport prevents stable charge accumulation in regions with high vertical electric fields, minimizing backside depletion, unlike during back-gating. Simultaneously, hole generation in the unintentionally doped GaN (GaN:uid) layer compensates for the RDS,on increase. These insights enable a comprehensive dynamic GaN-on-silicon (Si) buffer charging model that explains RDS,on drift under both back-gating and OFF-state stress conditions, addressing a critical gap in the understanding of GaN HEMT degradation. This work establishes a robust foundation for enhancing GaN HEMT performance and reliability. The developed measurement infrastructure and models provide practical insights for optimizing buffer design and advancing technology computer-aided design (TCAD) simulations. Ultimately, this research advances the robust deployment of GaN HEMTs in power conversion, enabling more energy-efficient, compact, and reliable technologies that benefit future electronic systems and reduce their environmental impact.
Boris Butej (Wed,) studied this question.