With the widespread deployment of SRAM-based FPGAs across multiple application scenarios, the soft error resilience of FPGAs has become critically important. To mitigate errors, current mainstream techniques either incur significant PPA (Performance, Power, Area) overhead or exhibit inadequate fault tolerance. Addressing this fault-tolerance–PPA trade-off, this study reduces resource consumption in Triple Modular Redundancy (TMR) implementations while deploying high-efficiency hardening methods at alternative granularity tiers. We propose a multi-tier spatiotemporal hardening framework and evaluation method (MSHE-SE), achieving two key contributions on a 70-million-gate FPGA platform: full-flow, full-granularity protection from RTL to post-physical-implementation netlists by integrating spatiotemporal methods across multiple FPGA EDA stages; and dual-mode fault injection validation utilizing synergistic JTAG and SEM mechanisms. A pseudo-random sequence generator emulates real-world environments to evaluate the system Mean Time Between Failures (MTBF) of FPGA designs. Finally, experimental results demonstrate that, compared to commercial TMR tools, the proposed method reduces LUT resource utilization by 10.9–45.7% and enhances system MTBF by an average factor of 18.28×.
Wang et al. (Wed,) studied this question.