A Kickback Noise Suppression Comparator for Single‐Slope ADCs in CMOS Image Sensors

ABSTRACT This brief presents a kickback noise suppression comparator for single‐slope (SS) analog‐to‐digital converter (ADC) in CMOS image sensors. The voltage clamping circuit, used for kickback noise suppression, comprises three transistors. By clamping the output of the first‐stage comparator when the comparator flips, it ensures that the input transistors operate in saturation region, thereby effectively preventing voltage jumps. The proposed SS ADC is designed with 110‐nm CMOS process. Post‐layout simulation results show that kickback noise is reduced to 75 V from 7.998 mV when 1000 columns of ADCs flip simultaneously. Compared to conventional SS ADCs, the proposed 11‐bit ADC reduces nonlinear error to below 1 LSB, with a minimal increase in power consumption (0.03 W) and area (50 m). The proposed ADC achieves DNL of +0.4/0.6 LSB and INL of 0.3/1.9 LSB. The simulation results show that the proposed comparator fundamentally suppresses the generation of kickback noise and improves the ramp linearity of SS ADC.