Soft errors pose a significant threat to the reliability of digital circuits, especially in harsh environments. While traditional error detection and correction techniques, such as Hamming codes and dual modular redundancy (DMR), have been widely employed, they often incur significant hardware overhead. This article presents a novel approach to enhancing the fault tolerance of finite impulse response (FIR) filters using multivalued logic (MVL). By leveraging the inherent redundancy of MVL, we propose several fault detection schemes based on current‐mode MVL (CMMVL). These proposed architectures offer a significant reduction in hardware overhead compared to state‐of‐the‐art techniques, often achieving at least a 60% decrease in area overhead. However, due to the power consumption characteristics of CMMVL, the proposed methods may introduce a higher power overhead. Among the proposed schemes, the time‐division multiplexed checker (TDMC), technique demonstrates on average a 30% reduction in power overhead compared to the best previous method. Our proposed architectures achieve an area overhead of less than 40%, a significant reduction compared to the 110% overhead of conventional DMR. Among these, the TDMC architecture also reduces power overhead to 77%, outperforming DMR’s 108% power overhead. However, due to the high delay of the checker circuit, our methods do not show a significant improvement in the power‐delay product (PDP). In the best‐case prelayout scenario, the TDMC overhead is similar to DMR. Unfortunately, in the post‐layout simulation, this overhead increases by as much as 110%.
Reza Omidi (Thu,) studied this question.