The increasing demand for effective and versatile processors has led to the introduction of open-source instruction set architectures such as RISC-V. Today’s software requires processors that support processing that involves both integer and floating point operations. Using the traditional method of carrying out these operations with separate hardware units consumes more power and complicates circuitry. In this paper, the development of a 32-bit RISC V processor with an FPU that operates in a dynamic way is presented. The processor has achieved effective resource utilization and power saving. This process is done using Verilog Hardware Description Language (HDL), where integer operations are carried out using the Arithmetic Logic Unit (ALU) while floating point operations are done by the Floating Point Unit (FPU). The operations involving floating point numbers follow IEEE standard 754 standard in its floating-point arithmetic processes.
Kumar et al. (Fri,) studied this question.