GEMA+: A Hardware Accelerator for Exact Sequence Mapping Using Learned Indexing with Reduced Sensitivity to Read Length

This paper presents the GEMA+ sequence mapping technique, characterized by its minimal sensitivity to the length of input read sequences. Unlike previously proposed methods, including GEMA and other similar learned index mapping techniques, GEMA+ effectively addresses the challenge of non-uniformity in the ascending trend of the mapping speed with the increasing read length. This challenge is tackled by our innovative process that eliminates the need for padding, which has traditionally been a source of performance variability. GEMA+ retains the efficient data structures of the original GEMA, ensuring no additional memory overhead. Additionally, we propose modifications to the hardware architecture of GEMA, resulting in an efficient implementation of GEMA+ on FPGA devices. The performance of the proposed technique is evaluated through post place-and-route simulations, which reveal that GEMA+ achieves a consistent and uniform increase in mapping speed as read length increases. By reducing performance sensitivity to input sequence length, GEMA+ demonstrates an average performance improvement of 42.5% for short reads and 11.8% for long reads, compared to the original GEMA.