Two-dimensional (2D) materials have emerged as promising candidates for next-generation semiconductors owing to their superior electrical and mechanical characteristics. However, conventional synthesis methods, such as chemical vapor deposition and mechanical exfoliation, face challenges in achieving the large-area scalability and efficiency required for high-performance logic devices. To address these issues, this study demonstrates a scalable manufacturing process utilizing electrochemical exfoliation. This cost-effective solution-based method facilitates the production of high-quality 2D nanosheets by weakening the interlayer van der Waals forces of bulk crystals. The resulting n-type MoS2 and p-type WSe2 inks were uniformly deposited via a large-area blade coating technique. To mitigate defects generated during exfoliation, we employed a chemical passivation treatment using bis(trifluoromethane)sulfonimide (TFSI). The fabricated MoS2 and WSe2 thin-film transistors exhibited enhanced electrical performance, with significant improvements in carrier mobility (up to 10 and 5 cm2 V−1 s−1, respectively) and on/off current ratios (exceeding 105). Furthermore, by integrating these optimized n-type and p-type channel devices, we successfully demonstrated functional CMOS inverter logic circuits with a gain of ∼6. These results suggest that combining electrochemical exfoliation, defect engineering via TFSI, and blade coating offers a viable pathway for realizing large-scale 2D integrated circuits.
Hong et al. (2026) studied this question.