PulseExploreJournal ClubDebatesTrendingResearchersJournals
Instagram
HomeExploreJournal ClubTrending
Synapse
⌘+K
Synapse
January 25, 2026ACM Transactions on Storage0 citations

Prefetching Mapping Table Entries for Faster Address Translation in DRAM-less SSDs

Prefetching Mapping Table Entries to Speed up Address Translation in DRAM-less SSDs

View Full Paper

Authors

ZSZhibing ShaJLJun LiJWJingchun Wu

Discussion

Loading...

Member takes

Overview

Demonstrates improved I/O performance in DRAM-less storage by prefetching mapping table entries, suggesting higher cache efficiency.

Key Points

  • The aim is to enhance address translation efficiency in DRAM-less SSDs by leveraging prefetching techniques.
  • Proposed prefetching of mapping table entries based on locality
  • Utilized a runs test indicator to assess adjacent entry loading
  • Implemented cache management strategies to optimize hit ratios
  • Increased mapping table entry hit ratio by 39.4%
  • Reduced overall I/O latency by 23.4% on average
  • Improved response times for subsequent address translation requests
Ask AI
Helpful
Bookmark
Share
View Full Paper

Cite This Study

Sha et al. (2026) studied this question.

synapsesocial.com/papers/6975b2eafeba4585c2d6e605https://doi.org/10.1145/3789202
Ask AI
Helpful
Bookmark
Share
View Full Paper