Implementation of Dynamic Logic Gates Using BIST Architecture for Effective Computing

The growing quantity of transistors on a chip combined with the shrinking feature size has created manufacturing problems and increased failure rates. Testing is therefore now essential to any Very Large Scale Integrated (VLSI) design. A large amount of the expenses associated with design, manufacturing, and servicing digital circuits are related to testing. The two main strategies used in design-for-test (DFT) to control test costs are Scan and Built-In Self-Test (BIST). As a result, this study proposes utilizing the BIST architecture to construct dynamic logic gates for efficient computation and fault coverage. The BIST approach, which combines testgeneration encoding and error correction, is used in the implementation of this project by Xilinx ISE Design Suite 13.4. This, when applied to a BIST architecture, allows for the same high fault coverage. In accordance with its greatest input priority, it outputs an encoder. The encoder and decoder exhibit very different behaviors. For a given encoded input line, it provides precisely one line high at the output. At different stages of the system, including the chip, controller, connection and disk, error correction is carried out. Ultimately, the test pattern is adjusted to produce every state, hence enhancing fault coverage. Tested on common combinational circuits, the suggested approach has produced encouraging results. This project improves the quality and performance of ICs while also reducing the time and cost required for testing and validation. Speed comparison is contrasted with conventional approach is 78% and Delay is 67%.