ABSTRACT A transistor with fully laminated plate‐type triode electrodes, source, drain and gate offers higher current density than a typical transistor design by allowing a 2D current path. Nanoscale transistors face challenges like off‐state leakage, so we introduce a new design using a laminated plate‐type architecture and a dual‐modulation strategy to improve performance and stability. Both top and bottom gates are used as active electrodes to fully control the channel's thickness. A micro‐hole patterned electrode is employed to enable effective gate field penetration into the channel, while a graphene electrode facilitates Fermi‐level modulation and improves field transfer. Furthermore, a leakage blocking layer is inserted to suppress unwanted carrier injection in the source and drain overlap regions. The device achieves low off‐state current of ≈10 −12 A and an on/off‐current ratio exceeding 10 6 at V DS of 3 V. It also delivers high output currents under low‐voltage operation (1 mA cm −2 at 0.1 V and 50 mA cm −2 at 1 V). Despite a nanoscale channel length, the device maintains near‐zero V TH . The fully encapsulated channel shows strong reliability against bias stress and light. This work shows that a laminated vertical design with dual‐gate control effectively enhances the stability of nanoscale transistors, highlighting their potential for next‐generation low‐power logic, memory, and flexible electronics.
Pyo et al. (2026) studied this question.