Yield and Cost Analysis of a Face-to-Back Chip-on-Wafer 3D Package

This paper will present a cost and yield breakdown of a 3D stack built using chip-on-wafer hybrid bonding in a face-to-back style process flow. The goal of this analysis is to understand the main cost drivers for this type of packaging. Activity based cost modeling will be used. This is a detailed, bottom-up approach to cost that breaks down the contribution of different types of cost for every step, such as material, labor, and capital. Factory-level parameters and yield are included as well. The scope of analysis includes the cost to process the incoming top wafer (which is ultimately diced and bonded in chip form), the cost of the bottom wafer, and the necessary processing both before and after bonding that ends with a die stack ready for placement. The cost of the incoming wafers is included as well in order to understand the impact of yield loss. Placing the die stack on an interposer or substrate is not part of this analysis.