This work was funded by the European Union, Horizon Europe program under grant agreement 101070417 (SPIDER project). For the required purpose of Open Access the author has applied a CC BY public copyright license to any Author Accepted Manuscript version arising from this submission. In a world with rapidly increasing energy consumption driven by big data and power hungry AI applications, the need to increase energy efficiency in computing gains more and more attention. A further downscaling of CMOS becomes more and more challenging with higher investment costs, hence new computing architectures are urgently sought after. Among alternatives to CMOS are spin wave devices based on majority gate logic (SWMG), in which magnetic spin waves interference and logic gates with more than two inputs are used. Investigations of these devices on the logic circuit level have been started not long ago. Studies show their potential for smaller area and lower power consumptions compared to CMOS. So far most of the research was done based on magnetic materials like YIG, CoFeB or permalloy as wave guides, often on special carrier materials like Gadolinium Gallium Garnet (GGG) to compose a spin wave chip. These novel materials in the field of device packaging may require new concepts of their handling and integration into a full system as well as investigations of the influences of the packaging on their performance. The approach of packaging a SWMG in a hybrid system with a CMOS is supposed to shows a first step on how to combine different computational architectures in order to combine their strength in future systems, e.g. approximate computing or AI optimized subsystems.
Lars Böttcher (Mon,) studied this question.