Simulation Study on the Scalability of Channel-All-Around Reconfigurable Field-Effect Transistors With Gate-Controlled Polarity

Conventional complementary metal oxide semiconductor (CMOS) devices rely heavily on doping, which increasingly limits scalability due to process constraints and performance degradations at advanced technology nodes. To overcome the drawbacks associated with doping, reconfigurable field-effect transistors (RFETs) that employ ferroelectric gate dielectrics with non-volatile programmability have emerged as a promising alternative for gate-controlled polarity modulation. Nevertheless, most reported RFETs adopt planar device geometries, raising concerns regarding their scalability at deeply scaled nodes. This work proposes a channel-all-around (CAA) RFETs architecture featuring gate-tunable polarity, based on an undoped WSe2 channel and an AlScN gate dielectric. Using calibrated TCAD simulations, we show that vertically stackable CAA structures, combined with intrinsically ambipolar WSe2, have significantly enhanced the scalability of RFETs for logic applications down to N0.5 technology node. Furthermore, the extracted device characteristics are implemented in a Verilog-A model for circuit-level simulations. The CAA-RFET-based complementary inverters exhibit robust noise margins, high voltage gains, and stable operation voltages at supply voltages down to 0.2 V. The reconfigurable CMOS logic gates with topologies identical to conventional CMOS designs, confirm the extreme scalability, and circuit-level viability of 2D CAA-RFETs for ultra-compact and energy-efficient programmable logic.