High-Efficiency MMIC GaN RF Power Amplifier With Improved Linearity in Series–Parallel Configuration

This paper presents a series-parallel RF power amplifier (PA) configuration with improved linearity performance achieved through an optimal combination of gate bias voltages and input power levels. The fundamental output voltage and the total third-order intermodulation distortion (IMD3) expressions of the series-parallel PA are analytically derived. Moreover, the proposed algorithm systematically determines optimal gate bias combinations for driver and power stages through comprehensive device characterization, harmonic balance simulations, and vector-based IMD3 cancellation analysis to maximize the achievable performance in terms of both linearity and efficiency. In addition, the fundamental and harmonic transconductances for different transistor active areas have been analyzed. This analysis determines the suitable number of gate fingers Nf and gate width Wf of the transistor in both driver and final stages to fulfill the required output power level, considering linearity and efficiency performance requirements. A 2-W X-band high linear and efficient RF PA is designed and fabricated in a 0.15-μm GaN-on-SiC process. A good agreement between simulations and measurements has been achieved. The continuous wave measurements of the proposed PA showed a power gain of 19 dB, a saturated output power level of more than 34-dBm, together with a power added efficiency (PAE) of 40% at 1-dB compression point. The two-tone signal measurements showed a similar gain level with a PAE of more than 37% at 33.5-dBm of output power. Moreover, the IMD3 is below -30-dBc while the PAE is greater than 33%. Modulated measurements using a 5-MHz WCDMA signal (PAPR=3.5 dB) confirmed the PA linearity improvement perfomance, showing an adjacent channel power ratio (ACPR) of -27 dBc and an error vector magnitude (EVM) between 1.9 and 5.1% across its output power range, making it suitable for high-order modulation schemes. The results validate the proposed design approach, offering competitive performance with respect to the actual state of the art 6G communication systems by balancing efficiency, linearity, and reliability.