Transmon Qubit Designs Toward Giga‐Scale Integration

Achieving practical quantum computers (PQCs) each based on millions and even billons of integrated quantum bits (qubits) is essential for tackling real-world computational tasks involving quantum phenomena at atomic and molecular levels 1, 2 such as drug discovery 3 and materials design 4; conventional supercomputers based on digital technology are inherently inefficient for such problems. Our recent analysis 5 of dimensional scalability for transmon qubit (i.e., transmission line shunted plasma oscillation qubit 6), which is today's leading quantum computing technology platform, highlights grand challenges and proposes likely solutions in implementing giga-scale qubit integration per chip necessary for building PQCs. The primary challenge with the current transmon design is its giant geometrical dimension with a large footprint up to 105 μm2 per qubit 7, essentially originating from the intrinsic need of large capacitors. Replacing the capacitors of distributed nature in the present transmon design with a compact parallel-plate capacitor of equivalent total capacitance using van der Waals materials has been shown to lead to an effective reduction of the qubit footprint by over 103 times 8. A similar reduction rate could also be achieved based on mature thin films used in advanced chip technologies such as the so-called high-κ dielectric materials 9, 10 as the insulting material in the parallel-plate capacitor. For instance, a parallel-plate capacitor of 1 pF capacitance, which is representative of that in today's transmon 5, with two electrodes sandwiching a 10-nm thick high-κ dielectric with a relative permittivity of 40 is 28 μm2 in size. To further reduce the capacitor size, an increase of the transmon qubit inductance could give rise to a proportional decrease of the capacitance 5 thereby giving rise to a further gain in qubit size reduction without affecting the operation of the transmon qubit itself. The result expressed in Equation (8) is informative. The highest gain is attained with α = 20, giving rise to in reducing the capacitor size from 28 μm2 to (28 μm2)/9.6 = 2.9 μm2 for l = w. Further, = 7.4 nA using Equation (6.1). With l = 10w that is readily achievable experimentally, the capacitor as well as the resultant qubit will be below 1 μm2 in size with = 23.6 nA. Note that these current values are substantially larger than that set by the requirement of EJ being greater than thermal energy kBT; according to Equation (3), (nA) 11, and it is equal to 1 nA at a typical qubit operation temperature of 25 mK. Thus, a chip area of 3 cm by 3 cm would suffice for the goal of integrating 109 qubits without considering wiring, etc. The derivations for transmon qubits above are also valid for gatemon 16, 17 (gate-tunable transmon) qubits. The core of a gatemon qubit is a Josephson junction field-effect transistor (JoFET) typically featuring superconducting source and drain contacts weakly linked by a semiconducting channel that in turn is electrostatically controlled by a gate electrode. The essence of gatemon qubits is, thus, the ability to control supercurrent-carrying carriers in Equation (6.3) by a third gate electrode 16, 17 in order to maximize χ without compromising the transmon operation. In comparison with transmon qubits, the added advantages of gatemon qubits are higher anharmonicity, free from bulky flux leads, and able to operate in the presence of magnetic field. Although experimental demonstrations of gatemon qubits were first realized using compound semiconductors 16-20, silicon-based JoFETs with the superconducting PtSi (platinum silicide) source and drain contacts have been demonstrated at research laboratories 21, 22. Furthermore, a CMOS-compatible process flow for large-scale JoFET fabrication has been outlined 23, and a self-aligned formation process protocol for integrating ultrathin (< 5 nm) superconducting PtSi films as the source and drain contacts developed 24. Therefore, two additional gatemon-based scalable qubit designs can be proposed: (1) the gatemon qubit with a JoFET replacing the twin superconducting Josephson junctions in the present-day transmon configuration but focusing on increasing its inductance and (2) a hybrid qubit by inserting a JoFET in series with the twin superconducting Josephson junctions, otherwise still in the present-day transmon configuration. Note that the JoFET inductance designed substantially larger than that of the transmon qubit will dominate. Shi-Li Zhang: conceptualization (lead), funding acquisition (lead), project administration (lead), resources (lead), data curation (lead), formal analysis (lead), investigation (lead), methodology (lead), validation (lead), writing – original draft (lead), writing – review and editing (lead). Yao Yao: data curation (supporting), formal analysis (supporting), investigation (supporting), methodology (supporting), validation (supporting), writing – review and editing (supporting). Ngan Pham: data curation (supporting), formal analysis (supporting), investigation (supporting), methodology (supporting), validation (supporting), writing – review and editing (supporting). Dongping Wu: conceptualization (supporting), formal analysis (supporting), validation (supporting), writing – review and editing (supporting). This study was partially financed by the Swedish Governmental Agency for Innovation Systems (Grant VINNOVA, 2024-00436) and the European QuantEra II Program (Grant 101017733) via the Swedish Research Council (Grant 2021-06025). The authors declare no conflicts of interest. All data are available in the main text.