Monolayer ScSI: An Excellent Performance Material for Sub-5 nm Transistors

As silicon-based field-effect transistors (FETs) approach their physical scaling limits, 2D semiconductors have emerged as promising alternative channel materials. This study employs an ab initio quantum transport method to simulate double-gate monolayer ScSI FETs with sub-5 nm gate length (Lg). Our findings demonstrate that ScSI devices with 5 nm Lg and underlaps (UL) of 0–3 nm, as well as 3 nm Lg with UL of 1–3 nm, satisfy the stringent 2028 high-performance targets of the International Technology Roadmap for Semiconductor (ITRS 2013) in terms of on-state current (Ion), power dissipation (PDP), and delay time (τ). Moreover, devices with 5 nm Lg (UL of 1–3 nm) and 3 nm Lg (UL of 2–3 nm) meet the low-power-dissipation requirements on Ion, τ, and PDP. Additionally, when incorporating negative capacitance technology, devices with 1 nm Lg and 2 or 3 nm UL also meet the high-performance ITRS requirements. These findings suggest that monolayer ScSI is a highly promising channel material for pushing Moore’s law scaling to sub-1 nm gate lengths.