3 A 500MS/s 12b Pipe-SAR ADC Using a Triple-Cascode FIA with Virtual Supply Extension

Key Points

• The aim is to present an efficient and linear 12-bit SAR ADC design using advanced amplifier techniques.
• Developed a 28 nm CMOS SAR ADC operating at 500 MS/s.
• Utilized a triple-cascode floating residue amplifier with virtual supply extension.
• Incorporated on-chip digital calibrations for performance enhancement.
• Achieved a signal-to-noise distortion ratio (SNDR) of 63.4 dB.
• Attained a spurious-free dynamic range (SFDR) of 81.0 dB at 240 MHz input.
• Consumed 6.64 mW of power and occupied a small area of 0.011 mm².

Abstract