This paper presents a 28 nm CMOS 500 MS/s 12b three-stage pipeline SAR ADC based on a triple-cascode single-stage floating residue amplifier with virtual supply extension to improve its efficiency and linearity. The ADC achieves 63.4 dB SNDR and 81.0 dB SFDR at 240 MHz input across PVT variations, consuming 6.64 mW with on-chip digital calibrations and occupying 0.011 mm2.
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Michele Rocco
Gabriele Zanoletti
Alessia Ceroni
Politecnico di Milano
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Rocco et al. (Sun,) studied this question.
www.synapsesocial.com/papers/69abc0925af8044f7a4e93df — DOI: https://doi.org/10.1109/isscc49663.2026.11409177