Low-temperature growth of L 2 1 -ordered Co2MnSi layers on sputtered Ge0.95Sn0.05(111)

Germanium–Tin (GeSn) alloys have a significant potential as next-generation electronic materials in the field of semiconductor technologies. In this study, to integrate spintronic technologies with next-generation semiconductor ones, we explore low-temperature growth of half-metallic Co 2 MnSi layers on sputtered Ge 0.95 Sn 0.05 (111) with an insertion of a ∼ 100-nm-thick Ge buffer layer on Si(111) substrates by molecular beam epitaxy. The surface roughness of the Ge 0.95 Sn 0.05 (111) layer derived from a large mismatch of ∼ 5 % between Ge 0.95 Sn 0.05 and Si is significantly decreased by CAtalyst Referred Etching with ruthenium, leading to a sufficiently flat Ge 0.95 Sn 0.05 (111) surface. As a result, on top of the flat Ge 0.95 Sn 0.05 (111) surface, an L 2 1 -ordered Co 2 MnSi layer is obtained at less than 80 °C with an insertion of a ∼ 1-nm-thick Fe layer. Because of the low-growth temperature, atomic interdiffusion between Co 2 MnSi and Ge 0.95 Sn 0.05 (111) and the surface segregation of Sn in the Ge 0.95 Sn 0.05 layer are suppressed. This study will pave the way toward the integration of high-performance spintronic technologies with group-IV semiconductor-based photonic and/or electronic devices on a Si platform.