Interleaved ASCON-128 Hardware Implementation for Multi-Channel IIoT Environments

Puntos clave

• This research aims to ensure data confidentiality and integrity in industrial IoT by implementing a hardware architecture based on ASCON-128.
• Propose an interleaved hardware architecture for ASCON-128-based encryption.
• Apply time-division multiplexing to handle 10 sensor channels with a single ASCON core.
• Implement a hardware scheduler for round-robin channel selection and context switching.
• Introduce a Per-Sample Nonce mode to prevent replay attacks.
• Achieved 100% match with 168 NIST SP 800-232 KAT test vectors.
• Utilized 1,847 ALM and 4 BRAM memory blocks in a 10-channel configuration.
• Attained 225 Mbps total throughput at 70.42 MHz operational frequency.
• Reduced resource usage by approximately 84% compared to dedicated core configurations.