Study on warpage stress in SiP packages during reflow soldering

With the ongoing trend toward miniaturization and high-density integration in electronic packaging, System-in-Package (SiP) has become a key research focus for large-scale AI model integration. This study investigates SiP packaging, focusing on warpage-induced stress during reflow soldering through detailed simulations. Unlike previous FEM approaches, this study integrates both viscoelastic dielectric modeling and trace mapping for realistic SiP reflow simulation, including actual copper trace layouts, viscoelasticity, and creep behavior, to develop an effective simulation model. Warpage and stress under complex conditions—such as varying dielectric layers, core substrate materials, and solder ball compositions—are thoroughly examined. The results indicate that simulations considering trace layouts and initial warpage offer significantly more accurate predictions than traditional models. For core substrate materials, the elastic modulus alone is not the dominant factor; rather, performance is governed by the interaction between the coefficient of thermal expansion (CTE) and interlayer compatibility. ABF-L engineering materials demonstrate minimal warpage when used as substrate dielectrics. Among solder materials, Sn63Pb37 exhibits the lowest equivalent stress at 29.007 MPa under identical conditions but accumulates the highest plastic strain at 6.3659 × 10−2, making it susceptible to plastic deformation. This compromises fatigue life and reliability, increasing the long-term risk of substrate warpage.