Reconfigurable constant multipliers: Hardware models, optimization algorithm and applications

This paper introduces a novel algorithm for building run-time reconfigurable single constant multipliers based on addition/subtraction, fixed bit-shift, and multiplexing. An exhaustive exploration of a wide design space using a mix of constraint programming, depth-first search, and branch-and-prune techniques ensures that the architectures are optimal in terms of hardware cost within their model. In this work, detailed bit-level cost models, both for ASIC and for FPGA, are defined and validated against actual syntheses. Compared to the state of the art, the proposed approach enables much larger constant sets and also significantly improves the performance of the resulting architectures. An application to quantized neural network inference demonstrates a reduction in multiplier area with no degradation in delay or accuracy.