A Highly Linear Passive Attenuator and Mixer Designs for an Observation Receiver in 130‐nm SOI CMOS

ABSTRACT In this paper, a highly linear passive attenuator and mixer are presented for use in an observation receiver path for digital predistortion (DPD) applications in a 130‐nm SOI CMOS process. This circuit operates at a carrier frequency of 5.9 GHz. The attenuator design comprises variable resistors, capacitors, and an on‐chip transformer design. The attenuator provides the ability to change the level of attenuation, spanning from 28 to 41 dB. This adjustment can be made in steps of 0.85 dB using a 4‐bit input control word. The mixer design employs a current‐mode double‐balanced passive topology to enhance linearity. The mixer design demonstrates a single‐sideband integrated noise figure of 29 dB with a total conversion gain of 2.8 dB. The value for the combined attenuator and mixer is recorded as 9.2 dBm in the observation receiver. The design consumes a total current of 7 mA from a 1.2‐V supply. The area of the designed circuit is 0.33 mm.