Timing and Power Optimization in Chiplet-Based SoCs with Heterogeneous Interconnects

The traditional architecture of System-on-Chip (SoC) has changed with the launch of chiplet-based architectures, enabling modular System-on-Chip integration and providing benefits in scalability, performance, and design flexibility.The review analyzes recent advances and the timing and power optimization problems of chiplet-based SoCs, particularly when heterogeneous interconnects are involved.Because chiplets may operate at different voltages, frequencies, and process nodes, timing synchronization and effective power distribution are essential.The article summarizes recent studies on modular AI acceleration, interconnect protocols, cost-performance trade-offs, and power management frameworks, with special emphasis on heterogeneous integration approaches such as 2.5D and 3D packaging.New tools and protocols, such as ChIP and decentralized power control mechanisms, are mentioned with respect to their role in reducing latency, energy consumption, and design complexity.Moreover, the article discusses developments in design automation and semiconductor technologies that support resilient timing closure and power optimization within multi-chiplet frameworks.The review indicates the significance of standardization, architectural codesign, and predictive EDA tools in realizing high-performance, energy-efficient chiplet-based SoCs suitable for nextgeneration computing systems.