Hardware‐Based On‐Chip Learning Using a Ferroelectric AND‐Type Array With Random Synaptic Weights

The growing complexity in machine learning has led to a rapid increase in model parameters, resulting in significant power consumption during large‐scale computations. Neuromorphic computing enables efficient in‐memory processing by reducing data movement through vector matrix multiplication. In this study, we propose a novel on‐chip learning scheme for ferroelectric AND‐type arrays by employing separate synaptic string arrays for forward and backward propagation. A HZO‐based FeAND array is fabricated, and selective programming, multilevel conductance tuning, and vector–matrix multiplication for neuromorphic applications are experimentally demonstrated in the HZO‐based FeAND array. To enable efficient on‐chip learning, a feedback alignment algorithm is adopted, which eliminates the need for weight transposition and significantly reduces the peripheral circuit complexity and energy consumption. Finally, the competitiveness of the proposed on‐chip learning method is verified by hardware‐aware on‐chip learning simulations reflecting the device characteristics.