Void-free Cu/dielectric hybrid bonding at low-temperature enabled by ultrathin metal passivation engineering for 3D-IC applications

Copper (Cu) surface topography, galvanic corrosion at the Cu-barrier interface and Cu-to-dielectric bonding primarily due to the misalignment are the present critical challenges in achieving void-free hybrid bonding. Additionally, Cu surface oxidation and dishing remain key bottlenecks in enabling reliable Cu interconnections at low temperatures in Cu/dielectric (SiO₂) hybrid bonding. To overcome these limitations, here we introduced a fabrication strategy that integrates an ultrathin metal (titanium (Ti)) passivation layer selectively engineered for Cu bond pads while maintaining compatibility with the damascene process. Despite the presence of the passivation layer, the observed Cu diffusion across the bonding interface and improved electrical contact resistance provides direct evidence of enhanced interfacial interdiffusion and oxidation resistance. This approach offers a scalable and effective solution for mitigating fundamental challenges in Cu/SiO₂ hybrid bonding and holds strong potential for integration into three-dimensional heterogeneous packaging technologies, enabling low thermal budget processing at ≤ 250 °C for ≤ 1-2 hour. Hemanth Kumar Cheemalamarri and colleagues report that Ultrathin Cu selective metal passivation enables void-free Cu/dielectric hybrid bonding by suppressing oxidation and topography nonuniformity, enhancing interfacial diffusion and electrical performance at ≤250 ˚C for next-generation 3D stacked high bandwidth memory.